전체 Analog Digital Communication Processor Memory Etc 제목 주저자 작성일 조회 45 DC to 50GHz SPDT switch in 28nm FD-SOI 김상민 25.05.01 37 44 외부 신호 주입을 통한 주파수 제어가 가능한 WR-3.4 발진기 도파관 모듈 고윤경 25.05.01 33 43 Design of a 15.4–17 GHz Current-Reused Coupled VCO and ImprovedNoise Circulati.. Aulya Sholehah Wataawa Sau 25.04.30 30 42 A High-Isolation Phase Conjugator for Retrodirective System Quang-Huy Do 25.04.30 39 41 Design of Radiation-Hardened Circuit Blocks in RF Transceiver 이종호 25.04.29 26 40 Design and Optimization of Radio-Frequency Receiver with Modified Genetic Algo.. 신호연 25.04.29 27 39 Design and Validation of Single-ended Sense Amplifier Utilizing Dummy Bit Line.. 김현진 25.04.29 37 38 Battery Measurement IC for Electric Vehicles using High-Resolution & High-Reli.. 김연홍 25.04.29 45 37 Design and Analysis of Reference-less Dynamic Comparator for PAM-4 Receiver 강태구 25.04.28 35 36 A TID and SEE Radiation-Hardened-by-Design Receiver 김태영 25.04.28 34 35 Design of Physically Unclonable Function Operation Circuit without Using a Ref.. 정준화 25.04.28 28 34 A 320-MS/s 2-b/cycle Second-order Noise-shaping SAR ADC Jiwoo Kim 25.04.28 53 33 A 25 Gb/s 850nm monolithic optical receiver with an on-chip Si APD bias contr.. Seung-Jae Yang 25.04.28 29 32 An Octave TR Quad-Core Quad-Mode VCO with Coupled Dual-Path Inductor 김현준 25.04.26 26 31 Highly Linear VMM Based on Charge Trap Device Using Bootstrapping and Non-Lin.. 최정인 25.04.25 32 30 A Low-Reference-Spur and Low-Jitter D-Band PLL with Complementary Power-Gating.. 김재호 25.04.25 34 29 A 0.097 mm2 4.0-31.8 GHz Inverter-based LNA With Parallel-Series Transformer F.. 성동현 25.04.24 70 28 A Low-Jitter Fractional-N Sampling PLL Using a Nonlinearity-Replication Techni.. 신유환 25.04.23 38 27 A 45-fsrms-Jitter D-Band Frequency Synthesizer Using a Subsampling PLL and a H.. 정서희 25.04.23 73 26 A High-power-density WR-3.4 Power Amplifier in 250-nm InP DHBT Technology Gunwoo Park 25.04.21 33 1 2 3 4 통합 검색어
