전체 Analog Digital Communication Processor Memory Etc 제목 주저자 작성일 조회 27 Calibration free Loop Unrolled SAR based Two-Step ADC with Time-Domain Backend 신현우 24.04.15 63 26 A PAM-4 Receiver with Selective Reference Voltage Adaptation for Strongness to.. 박정미 24.04.15 44 25 A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit 이윤상 24.04.11 75 24 Neural recording circuits resilient to multi-channel variation Jaeouk Cho 24.04.11 46 23 Transformer-based Injection-Locked Frequency Divider Sangmin Kim 24.04.11 62 22 A 300 GHz High-Power VCO Using Asymmetric Coupled Line 김현준 24.04.11 60 21 A Fully Integrated Dynamic-Voltage-Scaling Stimulator IC with Miniaturized Rec.. NGUYEN KIM HOANG 24.04.11 56 20 D-band Quadrature-Hybrid-Based Vector-Modulated Phase Shifter in 28-nm CMOS te.. Eunjung Kim 24.04.11 100 19 An Energy Efficient Multi-Channel Inductor-Based Stimulation System with Stimu.. Eojin Kim 24.04.11 58 18 ADC Utilizing Low Area Asynchronous Counter Gyeong-Bin Cho 24.04.11 51 17 Negative Voltage Multiplier in 28 nm CMOS Process 이재호 24.04.11 72 16 Frequency Analysis of Conventional and 3-Level Buck Converter Mun-Jung Cho 24.04.10 55 15 A Fully Integrated Microplastic Detection SoC with 0.1–3 GHz Bandwidth and 35 .. Seung-Beom Ku 24.04.09 62 14 A 24 Gb/s Receiver Using Duobinary Sampling for Sub-Baud-Rate CDR Seungwoo Park 24.04.09 58 13 A 25.2-Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achi.. 한찬흠 24.04.09 78 12 Design of a 16-Kb 1T1C DRAM for Conventional and Compute-in-Memory Access Mode.. 천현준 24.04.09 63 11 A 2.5-3.3V Input Highly Integrated Continuously-Scalable-Conversion-Ratio Reso.. Seokjin Kim 24.04.09 43 10 A 90.5% Peak Efficiency 12V-to-1V Fully Soft-Charging Hybrid Subtraction Mode .. 한석희 24.04.09 54 9 Closed-Loop Neural Interface Available Simultaneously Recording and Stimulatio.. Geunchang Seong 24.04.09 45 8 A 320-MS/s 2-b/cycle Second-order Noise-shaping SAR ADC InKwon Pack 24.04.08 58 1 2 3 통합 검색어
